Tony Cao aabfe31526 Enable EL6695 DC-Synchron mode (AssignActivate 0x320) ... - DC selection must use the structured <Dc><Data AssignActivate/> XSD element; legacy DcData hex writes get normalized to zeros by TwinCAT - TwinCAT converts it to DcData '2003...' (0x0320) on save: SYNC0/SYNC1 cyclic + SYNC0 activate for the bridge - Verified: clean activation, ticker OP, bSync=True, 90k cycles 0 errors, timing unchanged (jitter 7.3us mean) - docs: pitfall #10 (DC selection method)		2026-08-09 15:32:56 +08:00
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1kb-verification-progress.md	EL6695 8-byte bidirectional exchange with per-byte verification	2026-07-27 19:01:05 +08:00
8b-bridge-design.md	Enable EL6695 DC-Synchron mode (AssignActivate 0x320)	2026-08-09 15:32:56 +08:00
8b-test-report.md	800B PDO variant + long-term stability evidence + analysis docs	2026-08-06 01:10:50 +08:00
8b-verification-methodology.md	800B PDO variant + long-term stability evidence + analysis docs	2026-08-06 01:10:50 +08:00
500us-latency-plan.md	2kHz spin-lock mode: RTT halved to 2ms, per-byte XOR proof at 500us cycle	2026-07-28 00:11:34 +08:00
800b-pdo-plan.md	800B PDO variant + long-term stability evidence + analysis docs	2026-08-06 01:10:50 +08:00
d2000-dev-plan.md	D2000 (aarch64) migration: cross-build works with zero code changes	2026-08-06 02:05:05 +08:00
jitter-analysis.md	800B PDO variant + long-term stability evidence + analysis docs	2026-08-06 01:10:50 +08:00
scope-waveform-design.md	J1900 <-> TwinCAT 1 kHz verification over EL6695 bridge	2026-07-22 08:55:41 +08:00
verification-progress.md	EL6695 secondary side: SAFEOP/OP bring-up + 1kHz data loop	2026-07-23 00:46:48 +08:00