c3d9fb3708Cargo.lock: io-uring feature deps
d2000
Tony Cao
2026-08-12 23:17:35 +0800
9db5cf4504Full RT link verification report: methodology, metric analysis, 3h soak, RTT optimization, DC-Synchron findings
Tony Cao
2026-08-12 22:01:42 +0800
4083df04fbRTT optimization: 8kHz support, io_uring backend option (tested slower), RT-promote tx_rx thread; 8kHz RTT min 0.75ms mean 1.04ms
Tony Cao
2026-08-12 21:47:50 +0800
d95973ab68Soak sampler: add atomic nMatchLag freshness monitoring; add lag sampling script
Tony Cao
2026-08-12 17:39:50 +0800
253f4b3cf7J1900-side DC-Synchron: EL6695 secondary firmware sync_mode=2 via CoE, DC telemetry, verified 180s zero sync errors
Tony Cao
2026-08-10 01:56:41 +0800
cdb90c3e9aExtend async pipelined FPWR to 800B: 4kHz spin loop 2040->2960 cycles/s
Tony Cao
2026-08-10 01:28:43 +0800
aabfe31526Enable EL6695 DC-Synchron mode (AssignActivate 0x320)
Tony Cao
2026-08-09 15:32:56 +0800
3c4b6e6d54D2000 (aarch64) migration: cross-build works with zero code changes
Tony Cao
2026-08-06 02:05:05 +0800
f0163d8d70800B PDO variant + long-term stability evidence + analysis docs
Tony Cao
2026-08-06 01:10:50 +0800
8c1f519526Async pipelined FPWR + 4kHz: exec 245us->24us, RTT 2ms->1.25-1.5ms
Tony Cao
2026-07-28 01:18:05 +0800
3a26aea0822kHz spin-lock mode: RTT halved to 2ms, per-byte XOR proof at 500us cycle
Tony Cao
2026-07-28 00:11:34 +0800
309aaba342EL6695 8-byte bidirectional exchange with per-byte verification
Tony Cao
2026-07-27 19:01:05 +0800
2837f2a13dEL6695 secondary side: SAFEOP/OP bring-up + 1kHz data loop
Tony Cao
2026-07-23 00:46:48 +0800
21b2d3bf99J1900 <-> TwinCAT 1 kHz verification over EL6695 bridge
Tony Cao
2026-07-22 08:55:41 +0800