tonycao/ethercat-linux
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  • 98448182a8 rfm-ring: complete unreachable match arm d2000 Tony Cao 2026-09-24 15:44:14 +0800
  • 8dca6395d0 feat(rfm): add rfm-ring mode for one-shot PCIe ring-continuity check Tony Cao 2026-09-24 15:34:25 +0800
  • 3f29a86239 rfm-bridge: fix FPWR gating (was inside Mode::Ticker so bridge never wrote SM2), single-point f(x) on D2000, dumb reflector echo, REP budget 1.5ms Tony Cao 2026-09-24 15:12:43 +0800
  • b92484a86c rfm: multi-card --rfm-dev, ARM64 device-memory-safe bulk I/O, RT pinning, mailbox init Tony Cao 2026-09-21 19:02:20 +0800
  • e032f31392 feat(rfm): PCI-5565 reflective memory via VFIO/kernel-driver, ping/echo/bridge modes Tony Cao 2026-09-20 13:03:16 +0800
  • b30e183cd8 build: vendor crc32fast 1.5.0 for offline aarch64-musl cross build Tony Cao 2026-09-20 11:32:02 +0800
  • c3d9fb3708 Cargo.lock: io-uring feature deps Tony Cao 2026-08-12 23:17:35 +0800
  • 9db5cf4504 Full RT link verification report: methodology, metric analysis, 3h soak, RTT optimization, DC-Synchron findings Tony Cao 2026-08-12 22:01:42 +0800
  • 4083df04fb RTT optimization: 8kHz support, io_uring backend option (tested slower), RT-promote tx_rx thread; 8kHz RTT min 0.75ms mean 1.04ms Tony Cao 2026-08-12 21:47:50 +0800
  • d95973ab68 Soak sampler: add atomic nMatchLag freshness monitoring; add lag sampling script Tony Cao 2026-08-12 17:39:50 +0800
  • 253f4b3cf7 J1900-side DC-Synchron: EL6695 secondary firmware sync_mode=2 via CoE, DC telemetry, verified 180s zero sync errors Tony Cao 2026-08-10 01:56:41 +0800
  • cdb90c3e9a Extend async pipelined FPWR to 800B: 4kHz spin loop 2040->2960 cycles/s Tony Cao 2026-08-10 01:28:43 +0800
  • aabfe31526 Enable EL6695 DC-Synchron mode (AssignActivate 0x320) Tony Cao 2026-08-09 15:32:56 +0800
  • 3c4b6e6d54 D2000 (aarch64) migration: cross-build works with zero code changes Tony Cao 2026-08-06 02:05:05 +0800
  • f0163d8d70 800B PDO variant + long-term stability evidence + analysis docs Tony Cao 2026-08-06 01:10:50 +0800
  • 8c1f519526 Async pipelined FPWR + 4kHz: exec 245us->24us, RTT 2ms->1.25-1.5ms Tony Cao 2026-07-28 01:18:05 +0800
  • 3a26aea082 2kHz spin-lock mode: RTT halved to 2ms, per-byte XOR proof at 500us cycle Tony Cao 2026-07-28 00:11:34 +0800
  • 309aaba342 EL6695 8-byte bidirectional exchange with per-byte verification Tony Cao 2026-07-27 19:01:05 +0800
  • 2837f2a13d EL6695 secondary side: SAFEOP/OP bring-up + 1kHz data loop Tony Cao 2026-07-23 00:46:48 +0800
  • 21b2d3bf99 J1900 <-> TwinCAT 1 kHz verification over EL6695 bridge Tony Cao 2026-07-22 08:55:41 +0800