Tony Cao
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cdb90c3e9a
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Extend async pipelined FPWR to 800B: 4kHz spin loop 2040->2960 cycles/s
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2026-08-10 01:28:43 +08:00 |
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Tony Cao
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aabfe31526
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Enable EL6695 DC-Synchron mode (AssignActivate 0x320)
- DC selection must use the structured <Dc><Data AssignActivate/> XSD
element; legacy DcData hex writes get normalized to zeros by TwinCAT
- TwinCAT converts it to DcData '2003...' (0x0320) on save: SYNC0/SYNC1
cyclic + SYNC0 activate for the bridge
- Verified: clean activation, ticker OP, bSync=True, 90k cycles 0 errors,
timing unchanged (jitter 7.3us mean)
- docs: pitfall #10 (DC selection method)
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2026-08-09 15:32:56 +08:00 |
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Tony Cao
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3c4b6e6d54
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D2000 (aarch64) migration: cross-build works with zero code changes
- .cargo/config.toml: rust-lld linker pinned for x86_64 + aarch64 musl
targets (RUSTFLAGS no longer needed)
- scripts/d2000-deploy.ps1: build -> AArch64 ELF check -> scp deploy
- docs/d2000-dev-plan.md: M2 done; rustup mirror gotcha documented
(cached channel manifest pins absolute mirror URLs; patch it to
static.rust-lang.org when a component 404s)
- verified: target/aarch64-unknown-linux-musl/release/el6695-rt is a
static AArch64 ELF (e_machine=0xB7), ~1MB
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2026-08-06 02:05:05 +08:00 |
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Tony Cao
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f0163d8d70
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800B PDO variant + long-term stability evidence + analysis docs
- twin_layout_blob_sized generalized: multi-entry TwinCAT line format
(1 real @240bit + N continuation + remainder entry); 1024B path kept
byte-identical; 800B = 27 entries verified on hardware
- 800B constants (PAYLOAD/SM 800), deployed as el6695_rt_800b
- 10-min + 5h stability runs: 18M cycles, zero errors, zero mismatches,
PLC nMismatch frozen over the whole run (monitor_5h.csv evidence)
- docs: 800B plan/design/verification/test-report chapters,
jitter analysis (NFS rootfs stall primary cause), D2000 dev plan
- scripts: 800B deploy/relink/verify, mismatch-delta, 5h monitor
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2026-08-06 01:10:50 +08:00 |
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Tony Cao
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8c1f519526
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Async pipelined FPWR + 4kHz: exec 245us->24us, RTT 2ms->1.25-1.5ms
- FPWR fire-and-forget: two alternating leaked tx slots, or()-driven
20us kick to reach sendable, poll_once reap after next spin-detect
(late=0 over 350k cycles). Fixes: reap placement, poll_once kick
- exec drops to 24us mean, freeing budget for 4kHz (250us) operation
- 4kHz verified: TwinCAT PLC at 4001.8Hz, lag 5-6 cycles
(RTT 1.25-1.5ms); J1900 effective 2.9kHz - FPRD poll cost (71us x N)
exceeds 250us budget, occasional frame miss
- Conclusion: J1900 write wait never contributed to lag; the 4-stage
pipeline is TwinCAT IO mapping + bridge forwarding
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2026-07-28 01:18:05 +08:00 |
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Tony Cao
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3a26aea082
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2kHz spin-lock mode: RTT halved to 2ms, per-byte XOR proof at 500us cycle
- ticker: --spin mode polls FPRD until payload changes (phase-locks
processing to TwinCAT frame arrival instead of free-running ticker),
timeout at 1.5 periods keeps loop alive on master stop
- verified: 238k cycles, 0 errors, exec=245us (FPWR-bound),
TwinCAT PLC task confirmed at 2000.8 Hz (all three tasks 0.5ms;
base tick was already 50us - no base-time change needed)
- docs: 500us latency plan; scripts: task-rate ADS probe, 2kHz deploy,
UI automation experiments (pywinauto) for task cycle inspection
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2026-07-28 00:11:34 +08:00 |
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Tony Cao
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309aaba342
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EL6695 8-byte bidirectional exchange with per-byte verification
- 8B PDO config: ULINT-sized payload, no 0x1A01 diag PDO on SM3
(device rejected SM3=8 with diag assigned: 'size not allowed, min/max 0xa')
- twin_layout_blob_sized(): single 64-bit mapping entry for 8B payloads
- Ticker: per-byte XOR 0x5A transform in 8B mode so TwinCAT can verify
every byte individually (1KB path unchanged, const-guarded)
- TwinCAT automation scripts: deploy with RPC retry, LinkVariables-based
whole-array relink (element links only carry 1 byte), ADS watch, diag
- Docs: 8B design, verification methodology, test report
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2026-07-27 19:01:05 +08:00 |
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