Tony Cao
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8c1f519526
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Async pipelined FPWR + 4kHz: exec 245us->24us, RTT 2ms->1.25-1.5ms
- FPWR fire-and-forget: two alternating leaked tx slots, or()-driven
20us kick to reach sendable, poll_once reap after next spin-detect
(late=0 over 350k cycles). Fixes: reap placement, poll_once kick
- exec drops to 24us mean, freeing budget for 4kHz (250us) operation
- 4kHz verified: TwinCAT PLC at 4001.8Hz, lag 5-6 cycles
(RTT 1.25-1.5ms); J1900 effective 2.9kHz - FPRD poll cost (71us x N)
exceeds 250us budget, occasional frame miss
- Conclusion: J1900 write wait never contributed to lag; the 4-stage
pipeline is TwinCAT IO mapping + bridge forwarding
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2026-07-28 01:18:05 +08:00 |
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