Commit Graph

6 Commits

Author SHA1 Message Date
Tony Cao
3c4b6e6d54 D2000 (aarch64) migration: cross-build works with zero code changes
- .cargo/config.toml: rust-lld linker pinned for x86_64 + aarch64 musl
  targets (RUSTFLAGS no longer needed)
- scripts/d2000-deploy.ps1: build -> AArch64 ELF check -> scp deploy
- docs/d2000-dev-plan.md: M2 done; rustup mirror gotcha documented
  (cached channel manifest pins absolute mirror URLs; patch it to
  static.rust-lang.org when a component 404s)
- verified: target/aarch64-unknown-linux-musl/release/el6695-rt is a
  static AArch64 ELF (e_machine=0xB7), ~1MB
2026-08-06 02:05:05 +08:00
Tony Cao
f0163d8d70 800B PDO variant + long-term stability evidence + analysis docs
- twin_layout_blob_sized generalized: multi-entry TwinCAT line format
  (1 real @240bit + N continuation + remainder entry); 1024B path kept
  byte-identical; 800B = 27 entries verified on hardware
- 800B constants (PAYLOAD/SM 800), deployed as el6695_rt_800b
- 10-min + 5h stability runs: 18M cycles, zero errors, zero mismatches,
  PLC nMismatch frozen over the whole run (monitor_5h.csv evidence)
- docs: 800B plan/design/verification/test-report chapters,
  jitter analysis (NFS rootfs stall primary cause), D2000 dev plan
- scripts: 800B deploy/relink/verify, mismatch-delta, 5h monitor
2026-08-06 01:10:50 +08:00
Tony Cao
3a26aea082 2kHz spin-lock mode: RTT halved to 2ms, per-byte XOR proof at 500us cycle
- ticker: --spin mode polls FPRD until payload changes (phase-locks
  processing to TwinCAT frame arrival instead of free-running ticker),
  timeout at 1.5 periods keeps loop alive on master stop
- verified: 238k cycles, 0 errors, exec=245us (FPWR-bound),
  TwinCAT PLC task confirmed at 2000.8 Hz (all three tasks 0.5ms;
  base tick was already 50us - no base-time change needed)
- docs: 500us latency plan; scripts: task-rate ADS probe, 2kHz deploy,
  UI automation experiments (pywinauto) for task cycle inspection
2026-07-28 00:11:34 +08:00
Tony Cao
309aaba342 EL6695 8-byte bidirectional exchange with per-byte verification
- 8B PDO config: ULINT-sized payload, no 0x1A01 diag PDO on SM3
  (device rejected SM3=8 with diag assigned: 'size not allowed, min/max 0xa')
- twin_layout_blob_sized(): single 64-bit mapping entry for 8B payloads
- Ticker: per-byte XOR 0x5A transform in 8B mode so TwinCAT can verify
  every byte individually (1KB path unchanged, const-guarded)
- TwinCAT automation scripts: deploy with RPC retry, LinkVariables-based
  whole-array relink (element links only carry 1 byte), ADS watch, diag
- Docs: 8B design, verification methodology, test report
2026-07-27 19:01:05 +08:00
Tony Cao
2837f2a13d EL6695 secondary side: SAFEOP/OP bring-up + 1kHz data loop
- Fix SM ctrl bytes for SM2 (0x64) and SM3 (0x20) per ESI
- Add SM2/SM3 register config + FMMU + PDO assignment via SDO
- Change SM_TX_ADDR/RX_ADDR to SM2(0x1C00)/SM3(0x8E00)
- Add ensure_od_secondary for PDO assignment
- Add secondary-side diagnostics (CoE object probe)
- Update SM2/SM3 enable/disable sequence for clean config
- Add full bring-up sequence: INIT->PREOP->SAFEOP->OP
2026-07-23 00:46:48 +08:00
Tony Cao
21b2d3bf99 J1900 <-> TwinCAT 1 kHz verification over EL6695 bridge
Re-implementation of rustbootd's ecat_el6695_* examples as a single binary
with fixes found in review and on hardware:

- DC-follow PLL hardened against period-2 hunting: slew-limited anchor
  (+/-50us/cycle), bistable-trap snap re-anchor, re-prime on stale deadline
- drift-free absolute-grid ticker mode; probe mode for timestamp forensics
- bounded-memory online stats (histograms), graceful SIGINT/SIGTERM shutdown
  with full report, error-streak abort
- timestamp plausibility filter comparing against the previous raw sample
  (avoids the deadlock after a startup outlier)
- XFC scope waveform options: --el2202 (with --el2202-dual), --el2262,
  --el1252 latch timestamp readback with per-channel edge statistics
- register access unified in regs.rs: named bit constants everywhere,
  read-modify-write for enable/activation bytes
- vendored patched ethercrab 0.7.1 (sdo_write_complete, send_raw_coe)

Verified on J1900 (PREEMPT_RT 6.6.135): 600k cycles/600s exact 1 kHz,
tx/rx zero errors, phase_err p50=164us std=5us; EL2202<->EL1252 loopback
edge interval mean 2000.24us std=24.65us.
2026-07-22 08:55:41 +08:00