J1900-side DC-Synchron: EL6695 secondary firmware sync_mode=2 via CoE, DC telemetry, verified 180s zero sync errors
This commit is contained in:
Tony Cao
parent
cdb90c3e9a
commit
253f4b3cf7
180
src/main.rs
180
src/main.rs
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@ -98,6 +98,9 @@ struct Config {
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/// payload changes (new TwinCAT frame), then process immediately.
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/// Phase-locks J1900 processing to the primary master's frame arrival.
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spin: bool,
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/// Enable DC SYNC0 on the EL6695 secondary (cycle = --cycle-us) and print
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/// per-second DC phase/drift telemetry in the report line.
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dc: bool,
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}
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fn parse_args() -> Result<Config, String> {
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@ -116,6 +119,7 @@ fn parse_args() -> Result<Config, String> {
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el2262: false,
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el1252_every: 1,
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spin: false,
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dc: false,
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};
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let mut args = std::env::args().skip(1).peekable();
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if let Some(a) = args.peek() {
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@ -146,6 +150,7 @@ fn parse_args() -> Result<Config, String> {
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"--prio" => cfg.prio = val("--prio")?.parse().map_err(|_| "bad --prio")?,
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"--quiet" => cfg.quiet = true,
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"--spin" => cfg.spin = true,
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"--dc" => cfg.dc = true,
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"--el2202" => cfg.el2202 = true,
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"--el2202-dual" => {
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cfg.el2202 = true;
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@ -525,6 +530,148 @@ async fn run(cfg: &Config) -> Result<(), Box<dyn std::error::Error>> {
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}
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println!(" >>> OP achieved! <<<");
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// ---- Optional DC SYNC0 on the EL6695 secondary ----
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// ethercrab init already distributed the system time (offset/propagation
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// delay/static drift). Here we only start the SYNC0 unit on --cycle-us
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// grid and verify the clock actually advances.
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let mut dc_ref: Option<(u64, u64)> = None; // (dc_time, mono_time) at setup
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if cfg.dc {
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let t1 = ethercrab::Command::fprd(station, regs::DC_SYSTEM_TIME)
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.receive::<u64>(&maindevice)
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.await
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.unwrap_or(0);
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std::thread::sleep(Duration::from_millis(100));
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let t2 = ethercrab::Command::fprd(station, regs::DC_SYSTEM_TIME)
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.receive::<u64>(&maindevice)
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.await
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.unwrap_or(0);
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let adv = t2.wrapping_sub(t1);
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println!("DC system time: {} -> {} (adv {} ns in 100ms)", t1, t2, adv);
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if adv < 50_000_000 || adv > 500_000_000 {
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println!("DC: clock not advancing sanely; SYNC0 setup skipped");
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} else {
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// Diagnostics: which DC register groups actually exist?
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for (reg, name) in [
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(0x0900u16, "rx_time_port0(u32)"),
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(0x0920u16, "sys_time_offset(u64)"),
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(0x0928u16, "prop_delay(u32)"),
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(0x0930u16, "drift... (u16)"),
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(0x0980u16, "sync_activation(u8)"),
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(0x0981u16, "sync_active_byte(u8)"),
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(0x09A0u16, "sync0_cycle(u32)"),
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(0x09AEu16, "sync0_status(u8)"),
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] {
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match ethercrab::Command::fprd(station, reg)
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.receive_slice(&maindevice, 8)
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.await
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{
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Ok(pdu) => {
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let raw: &[u8] = &pdu;
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println!(" DC probe 0x{:04X} {}: {:02X?}", reg, name, &raw[..8.min(raw.len())]);
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}
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Err(e) => println!(" DC probe 0x{:04X} {}: ERR {:?}", reg, name, e),
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}
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}
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// CoE view: 0x1C32 (SM2 outputs) / 0x1C33 (SM3 inputs) sync params
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for idx in [0x1C32u16, 0x1C33] {
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let n = sd.sdo_read::<u8>(idx, 0).await.unwrap_or(0xFF);
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println!(" CoE 0x{:04X}: {} subentries", idx, n);
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for (sub, name) in [(0x01u8, "sync_mode"), (0x04, "modes_supported"), (0x0B, "sm_event_missed"), (0x0C, "cycle_exceeded")] {
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match sd.sdo_read::<u16>(idx, sub).await {
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Ok(x) => println!(" CoE 0x{:04X}:{:02X} {} = 0x{:04X}", idx, sub, name, x),
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Err(e) => println!(" CoE 0x{:04X}:{:02X} {} ERR {:?}", idx, sub, name, e),
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}
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}
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match sd.sdo_read::<u32>(idx, 0x02).await {
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Ok(x) => println!(" CoE 0x{:04X}:02 cycle_time_ns = {}", idx, x),
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Err(e) => println!(" CoE 0x{:04X}:02 cycle_time_ns ERR {:?}", idx, e),
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}
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match sd.sdo_read::<u8>(idx, 0x20).await {
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Ok(x) => println!(" CoE 0x{:04X}:20 sync_error = {}", idx, x),
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Err(e) => println!(" CoE 0x{:04X}:20 sync_error ERR {:?}", idx, e),
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}
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}
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let start = t2.wrapping_add(100_000_000);
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let w1 = ethercrab::Command::fpwr(station, regs::DC_SYNC_START_TIME)
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.send(&maindevice, start)
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.await;
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println!(" DC write start_time(0x0990): {:?}", w1.as_ref().map(|_| "OK").map_err(|e| format!("{:?}", e)));
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let w2 = ethercrab::Command::fpwr(station, regs::DC_SYNC0_CYCLE)
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.send(&maindevice, cycle_ns as u32)
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.await;
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println!(" DC write sync0_cycle(0x09A0): {:?}", w2.as_ref().map(|_| "OK").map_err(|e| format!("{:?}", e)));
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let w3 = regs::rmw_u8(
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&maindevice,
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station,
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regs::DC_SYNC_ACTIVATION,
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regs::DC_SYNC0_ACTIVATE,
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0,
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)
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.await;
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println!(" DC rmw activation(0x0980): {:?}", w3.as_ref().map(|v| format!("0x{:02X}", v)).map_err(|e| format!("{:?}", e)));
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// rmw needs a read (fails here); try a blind full-byte write instead
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let w4 = ethercrab::Command::fpwr(station, regs::DC_SYNC_ACTIVATION)
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.send(&maindevice, regs::DC_SYNC0_ACTIVATE)
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.await;
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println!(" DC blind write activation(0x0980)=0x01: {:?}", w4.as_ref().map(|_| "OK").map_err(|e| format!("{:?}", e)));
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std::thread::sleep(Duration::from_millis(150));
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// Try selecting DC-Synchron SYNC0 via firmware object (mode 2).
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// May be rejected in OP; worth observing the abort code either way.
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let mut coe_dc_ok = true;
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for idx in [0x1C32u16, 0x1C33] {
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match sd.sdo_write::<u16>(idx, 0x01, 2).await {
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Ok(_) => println!(" CoE write 0x{:04X}:01 sync_mode=2 OK", idx),
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Err(e) => {
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coe_dc_ok = false;
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println!(" CoE write 0x{:04X}:01 sync_mode=2 ERR {:?}", idx, e);
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}
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}
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match sd.sdo_read::<u16>(idx, 0x01).await {
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Ok(x) => println!(" CoE-after 0x{:04X}:01 sync_mode = {}", idx, x),
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Err(e) => {
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coe_dc_ok = false;
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println!(" CoE-after 0x{:04X}:01 sync_mode ERR {:?}", idx, e);
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}
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}
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}
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if coe_dc_ok {
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let t_dc = ethercrab::Command::fprd(station, regs::DC_SYSTEM_TIME)
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.receive::<u64>(&maindevice)
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.await
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.unwrap_or(0);
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dc_ref = Some((t_dc, rt::now_ns()));
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println!("DC-Synchron: firmware sync_mode=2 accepted, DC telemetry on");
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}
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let act = ethercrab::Command::fprd(station, regs::DC_SYNC_ACTIVATION)
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.receive::<u8>(&maindevice)
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.await;
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let cyc0 = ethercrab::Command::fprd(station, regs::DC_SYNC0_CYCLE)
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.receive::<u32>(&maindevice)
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.await;
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let t3 = ethercrab::Command::fprd(station, regs::DC_SYSTEM_TIME)
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.receive::<u64>(&maindevice)
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.await
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.unwrap_or(0);
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let (al, alc) = bridge::drive_state(&maindevice, station, 0x0008).await;
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println!(" AL after DC writes: {}", bridge::verdict(al, alc));
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println!(
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"DC SYNC0: act={:?} cycle={:?} start=+100ms (t3={} start_delta={}ns)",
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act.as_ref().map(|v| format!("0x{:02X}", v)).map_err(|e| format!("{:?}", e)),
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cyc0.as_ref().map_err(|e| format!("{:?}", e)),
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t3,
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t3.wrapping_sub(start) as i64
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);
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if matches!(act, Ok(a) if a & regs::DC_SYNC0_ACTIVATE != 0)
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&& matches!(cyc0, Ok(c) if c == cycle_ns as u32)
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{
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dc_ref = Some((t3, rt::now_ns()));
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println!("DC SYNC0: active on EL6695 secondary");
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} else {
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println!("DC SYNC0: readback mismatch; running without DC telemetry");
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}
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}
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}
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// ---- Optional EL2202 oscilloscope waveform (toggle one DO per cycle) ----
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const EL2202_OUT_ADDR: u16 = 0x0F00;
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let mut el2202: Option<(u16, u16)> = None;
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@ -1109,8 +1256,23 @@ async fn run(cfg: &Config) -> Result<(), Box<dyn std::error::Error>> {
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}
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let proc_val = tc_seq.wrapping_mul(7).wrapping_add(3);
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let stale_pct = if cyc > 0 { (rx_stale * 100 / cyc) } else { 0 };
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let mut dc_info = String::new();
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if let Some((dc0, mono0)) = dc_ref {
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if let Ok(dc_now) = ethercrab::Command::fprd(station, regs::DC_SYSTEM_TIME)
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.receive::<u64>(&maindevice)
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.await
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{
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let mono_now = rt::now_ns();
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let drift = (dc_now.wrapping_sub(dc0)) as i64 - (mono_now - mono0) as i64;
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dc_info = format!(
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" dcph={} dcdr={}ns",
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dc_now % cycle_ns,
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drift
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);
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}
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}
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println!(
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"S tms={} cyc={} raw={} proc={} txe={} rxe={} late={} stale={}% mono={} cerr={} mism={} e0={} e1={}",
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"S tms={} cyc={} raw={} proc={} txe={} rxe={} late={} stale={}% mono={} cerr={} mism={} e0={} e1={}{}",
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start.elapsed().as_millis(),
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cyc,
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tc_seq,
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@ -1124,6 +1286,7 @@ async fn run(cfg: &Config) -> Result<(), Box<dyn std::error::Error>> {
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payload_mismatch,
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pos_edges,
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pos1_edges,
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dc_info,
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);
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last_report = Instant::now();
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}
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@ -1138,6 +1301,21 @@ async fn run(cfg: &Config) -> Result<(), Box<dyn std::error::Error>> {
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let _ = f.await;
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}
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// ---- DC post-run: re-read firmware sync counters accumulated during the run ----
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if cfg.dc {
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println!("\n=== DC post-run sync counters (0x1C32 SM2 / 0x1C33 SM3) ===");
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for idx in [0x1C32u16, 0x1C33] {
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let mode = sd.sdo_read::<u16>(idx, 0x01).await.unwrap_or(0xFFFF);
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let missed = sd.sdo_read::<u16>(idx, 0x0B).await.unwrap_or(0xFFFF);
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let exceeded = sd.sdo_read::<u16>(idx, 0x0C).await.unwrap_or(0xFFFF);
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let serr = sd.sdo_read::<u8>(idx, 0x20).await.unwrap_or(0xFF);
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println!(
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" 0x{:04X}: sync_mode={} sm_event_missed={} cycle_exceeded={} sync_error={}",
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idx, mode, missed, exceeded, serr
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);
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}
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}
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// ---- Final report ----
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println!("\n=== timing stats ===");
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jitter_st.report(1000, "us");
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